From 49df8ea93ed532874bd5b9b329fc246b349d9a65 Mon Sep 17 00:00:00 2001
From: d6 <d_m@plastic-idolatry.com>
Date: Mon, 7 Feb 2022 22:28:01 -0500
Subject: [PATCH] move tmp vars behind @m32 label

---
 math32.tal | 96 +++++++++++++++++++++++++++---------------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/math32.tal b/math32.tal
index e459c6b..9e54484 100644
--- a/math32.tal
+++ b/math32.tal
@@ -170,10 +170,10 @@
 
 ( temporary registers )
 ( shared by most operations, except mul32 and div32 )
-[ @x0 $1 @x1 $1 @x2 $1 @x3 $1
-  @y0 $1 @y1 $1 @y2 $1 @y3 $1
-  @z0 $1 @z1 $1 @z2 $1 @z3 $1
-  @w0 $1 @w1 $1 @w2 $2 ]
+@m32 [ &x0 $1 &x1 $1 &x2 $1 &x3 $1
+       &y0 $1 &y1 $1 &y2 $1 &y3 $1
+       &z0 $1 &z1 $1 &z2 $1 &z3 $1
+       &w0 $1 &w1 $1 &w2 $2 ]
 
 ( bit shifting )
 
@@ -187,27 +187,27 @@
 
 ( shift right by 0-7 bits )
 @rshift32-0 ( x** n^ -> x<<n )
-        STHk  SFT                      ;z3 STA  ( write z3 )
-    #00 STHkr SFT2 #00 ;z3 LDA ORA2 ;z2 STA2 ( write z2,z3 )
-    #00 STHkr SFT2 #00 ;z2 LDA ORA2 ;z1 STA2 ( write z1,z2 )
-    #00 STHr  SFT2 #00 ;z1 LDA ORA2             ( compute z0,z1 )
-    ;z2 LDA2
+        STHk  SFT                      ;m32/z3 STA  ( write z3 )
+    #00 STHkr SFT2 #00 ;m32/z3 LDA ORA2 ;m32/z2 STA2 ( write z2,z3 )
+    #00 STHkr SFT2 #00 ;m32/z2 LDA ORA2 ;m32/z1 STA2 ( write z1,z2 )
+    #00 STHr  SFT2 #00 ;m32/z1 LDA ORA2             ( compute z0,z1 )
+    ;m32/z2 LDA2
     RTN
 
 ( shift right by 8-15 bits )
 @rshift32-1 ( x** n^ -> x<<n )
     #08 SUB STH POP 
-        STHkr SFT                      ;z3 STA  ( write z3 )
-    #00 STHkr SFT2 #00 ;z3 LDA ORA2 ;z2 STA2 ( write z2,z3 )
-    #00 STHr  SFT2 #00 ;z2 LDA ORA2             ( compute z1,z2 )
-    #00 TOR ;z3 LDA
+        STHkr SFT                      ;m32/z3 STA  ( write z3 )
+    #00 STHkr SFT2 #00 ;m32/z3 LDA ORA2 ;m32/z2 STA2 ( write z2,z3 )
+    #00 STHr  SFT2 #00 ;m32/z2 LDA ORA2             ( compute z1,z2 )
+    #00 TOR ;m32/z3 LDA
     RTN
 
 ( shift right by 16-23 bits )
 @rshift32-2 ( x** n^ -> x<<n )
     #10 SUB STH POP2
-        STHkr SFT                      ;z3 STA ( write z3 )
-    #00 STHr  SFT2 #00 ;z3 LDA ORA2            ( compute z2,z3 )
+        STHkr SFT                      ;m32/z3 STA ( write z3 )
+    #00 STHr  SFT2 #00 ;m32/z3 LDA ORA2            ( compute z2,z3 )
     #0000 SWP2
     RTN
 
@@ -229,30 +229,30 @@
 ( shift left by 0-7 bits )
 @lshift32-0 ( x** n^ -> x<<n )
     #40 SFT STH ( stash n<<4 )
-    #00 SWP STHkr SFT2                     ;z2 STA2 ( store z2,z3 )
-    #00 SWP STHkr SFT2 #00 ;z2 LDA ORA2 ;z1 STA2 ( store z1,z2 )
-    #00 SWP STHkr SFT2 #00 ;z1 LDA ORA2 ;z0 STA2 ( store z0,z1 )
-            STHr  SFT      ;z0 LDA ORA              ( calculate z0 )
-    ;z1 LDA ;z2 LDA2
+    #00 SWP STHkr SFT2                     ;m32/z2 STA2 ( store z2,z3 )
+    #00 SWP STHkr SFT2 #00 ;m32/z2 LDA ORA2 ;m32/z1 STA2 ( store z1,z2 )
+    #00 SWP STHkr SFT2 #00 ;m32/z1 LDA ORA2 ;m32/z0 STA2 ( store z0,z1 )
+            STHr  SFT      ;m32/z0 LDA ORA              ( calculate z0 )
+    ;m32/z1 LDA ;m32/z2 LDA2
     RTN
 
 ( shift left by 8-15 bits )
 @lshift32-1 ( x** n^ -> x<<n )
     #08 SUB #40 SFT STH ( stash [n-8]<<4 )
-    #00 SWP STHkr SFT2                     ;z1 STA2 ( store z1,z2 )
-    #00 SWP STHkr SFT2 #00 ;z1 LDA ORA2 ;z0 STA2 ( store z0,z1 )
-            STHr  SFT      ;z0 LDA ORA              ( calculate z0 )
+    #00 SWP STHkr SFT2                     ;m32/z1 STA2 ( store z1,z2 )
+    #00 SWP STHkr SFT2 #00 ;m32/z1 LDA ORA2 ;m32/z0 STA2 ( store z0,z1 )
+            STHr  SFT      ;m32/z0 LDA ORA              ( calculate z0 )
     SWP POP ( x0 unused )
-    ;z1 LDA2 #00
+    ;m32/z1 LDA2 #00
     RTN
 
 ( shift left by 16-23 bits )
 @lshift32-2 ( x** n^ -> x<<n )
     #10 SUB #40 SFT STH ( stash [n-16]<<4 )
-    #00 SWP STHkr SFT2                ;z0 STA2 ( store z0,z1 )
-            STHr  SFT  ;z0 LDA ORA             ( calculate z0 )
+    #00 SWP STHkr SFT2                ;m32/z0 STA2 ( store z0,z1 )
+            STHr  SFT  ;m32/z0 LDA ORA             ( calculate z0 )
     STH POP2 STHr
-    ;z1 LDA #0000
+    ;m32/z1 LDA #0000
     RTN
 
 ( shift left by 24-31 bits )
@@ -266,27 +266,27 @@
 
 ( x + y )
 @add32 ( xhi* xlo* yhi* ylo* -> zhi* zlo* )
-    ;y2 STA2 ;y0 STA2 ( save ylo, yhi )
-    ;x2 STA2 ;x0 STA2 ( save xlo, xhi )
-    #0000 #0000 ;z0 STA2 ;z2 STA2 ( reset zhi, zlo )
+    ;m32/y2 STA2 ;m32/y0 STA2 ( save ylo, yhi )
+    ;m32/x2 STA2 ;m32/x0 STA2 ( save xlo, xhi )
+    #0000 #0000 ;m32/z0 STA2 ;m32/z2 STA2 ( reset zhi, zlo )
 
     ( x3 + y3 => z2z3 )
-    #00 ;x3 LDA #00 ;y3 LDA ADD2 ;z2 STA2
+    #00 ;m32/x3 LDA #00 ;m32/y3 LDA ADD2 ;m32/z2 STA2
 
     ( x2 + y2 + z2 => z1z2 )
-    #00 ;x2 LDA ;z1 LDA2 ADD2 ;z1 STA2
-    #00 ;y2 LDA ;z1 LDA2 ADD2 ;z1 STA2
+    #00 ;m32/x2 LDA ;m32/z1 LDA2 ADD2 ;m32/z1 STA2
+    #00 ;m32/y2 LDA ;m32/z1 LDA2 ADD2 ;m32/z1 STA2
 
     ( x1 + y1 + z1 => z0z1 )
-    #00 ;x1 LDA ;z0 LDA2 ADD2 ;z0 STA2
-    #00 ;y1 LDA ;z0 LDA2 ADD2 ;z0 STA2
+    #00 ;m32/x1 LDA ;m32/z0 LDA2 ADD2 ;m32/z0 STA2
+    #00 ;m32/y1 LDA ;m32/z0 LDA2 ADD2 ;m32/z0 STA2
 
     ( x0 + y0 + z0 => z0 )
-    ;x0 LDA ;z0 LDA ADD ;z0 STA
-    ;y0 LDA ;z0 LDA ADD ;z0 STA
+    ;m32/x0 LDA ;m32/z0 LDA ADD ;m32/z0 STA
+    ;m32/y0 LDA ;m32/z0 LDA ADD ;m32/z0 STA
 
     ( load zhi,zlo )
-    ;z0 LDA2 ;z2 LDA2
+    ;m32/z0 LDA2 ;m32/z2 LDA2
     RTN
 
 ( -x )
@@ -305,26 +305,26 @@
 
 ( 16-bit multiplication )
 @mul16 ( x* y* -> z** )
-    ;y1 STA ;y0 STA ( save ylo, yhi )
-    ;x1 STA ;x0 STA ( save xlo, xhi )
-    #0000 #00 ;z1 STA2 ;z3 STA ( reset z1,z2,z3 )
-    #0000 #00 ;w0 STA2 ;w2 STA ( reset w0,w1,w2 )
+    ;m32/y1 STA ;m32/y0 STA ( save ylo, yhi )
+    ;m32/x1 STA ;m32/x0 STA ( save xlo, xhi )
+    #0000 #00 ;m32/z1 STA2 ;m32/z3 STA ( reset z1,z2,z3 )
+    #0000 #00 ;m32/w0 STA2 ;m32/w2 STA ( reset w0,w1,w2 )
 
     ( x1 * y1 => z1z2 )
-    #00 ;x1 LDA #00 ;y1 LDA MUL2 ;z2 STA2
+    #00 ;m32/x1 LDA #00 ;m32/y1 LDA MUL2 ;m32/z2 STA2
 
     ( x0 * y1 => z0z1 )
-    #00 ;x0 LDA #00 ;y1 LDA MUL2 ;z1 LDA2 ADD2 ;z1 STA2
+    #00 ;m32/x0 LDA #00 ;m32/y1 LDA MUL2 ;m32/z1 LDA2 ADD2 ;m32/z1 STA2
 
     ( x1 * y0 => w1w2 )
-    #00 ;x1 LDA #00 ;y0 LDA MUL2 ;w1 STA2
+    #00 ;m32/x1 LDA #00 ;m32/y0 LDA MUL2 ;m32/w1 STA2
 
     ( x0 * y0 => w0w1 )
-    #00 ;x0 LDA #00 ;y0 LDA MUL2 ;w0 LDA2 ADD2 ;w0 STA2
+    #00 ;m32/x0 LDA #00 ;m32/y0 LDA MUL2 ;m32/w0 LDA2 ADD2 ;m32/w0 STA2
 
     ( add z and a<<8 )
-    #00 ;z1 LDA2 ;z3 LDA
-    ;w0 LDA2 ;w2 LDA #00
+    #00 ;m32/z1 LDA2 ;m32/z3 LDA
+    ;m32/w0 LDA2 ;m32/w2 LDA #00
     ;add32 JSR2
     RTN