From 8c67cae39a7f34586e54f67220d18ef32b9dc389 Mon Sep 17 00:00:00 2001
From: d6 <d_m@plastic-idolatry.com>
Date: Thu, 23 Dec 2021 00:43:10 -0500
Subject: [PATCH] start on 32-bit math

---
 math32.tal | 189 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 189 insertions(+)
 create mode 100644 math32.tal

diff --git a/math32.tal b/math32.tal
new file mode 100644
index 0000000..a3459f4
--- /dev/null
+++ b/math32.tal
@@ -0,0 +1,189 @@
+( math32.tal )
+( )
+( 32-bit integers are represented by two 16-bit integers )
+( x** means xhi* xlo* )
+
+%DEBUG { #ff #0e DEO }
+%RTN  { JMP2r }
+%EMIT { #18 DEO }
+%DIGIT { #00 SWP ;digits ADD2 LDA EMIT }
+%SPACE { #20 EMIT }
+%NEWLINE { #0a EMIT }
+
+%TOR2 { ROT2 ROT2 }
+%POP4 { POP2 POP2 }
+
+%X { #0000 #0001 }
+%Y { #1234 #ffff }
+%Z { #fedc #ba98 }
+
+|0100
+    #ffff #ffff ;mul16 JSR2 ;emit-long JSR2 NEWLINE
+    #ffff #ffff #ffff #ffff ;mul32 JSR2 ;emit-long JSR2 NEWLINE
+
+    X Y #2b ;add32 ;emit-long ;test JSR2
+    Z Y #2b ;add32 ;emit-long ;test JSR2
+    #fedc #0000 #1234 #0000 #2b ;add32 ;emit-long ;test JSR2
+    #fedc #0000 #0000 #0000 #2b ;add32 ;emit-long ;test JSR2
+    #0000 #0000 #0000 #0000 #2b ;add32 ;emit-long ;test JSR2
+    X Y #26 ;and32 ;emit-long ;test JSR2
+    X Y #7c ;or32 ;emit-long ;test JSR2
+    X Y #5e ;xor32 ;emit-long ;test JSR2
+    X Y #3d ;eq32 ;emit-byte ;test JSR2
+    Y Y #3d ;eq32 ;emit-byte ;test JSR2
+    X Y #7e ;ne32 ;emit-byte ;test JSR2
+    X X #7e ;ne32 ;emit-byte ;test JSR2
+BRK
+
+@test ( x** y** symbol^ test-addr* emit-addr* -> )
+    ,&emitaddr STR2
+    ,&testaddr STR2
+    ,&testsym STR
+    ,&ylo STR2 ,&yhi STR2
+    ,&xlo STR2 ,&xhi STR2
+    ,&xhi LDR2 ,&xlo LDR2 ;emit-long JSR2
+    SPACE ,&testsym LDR EMIT SPACE
+    ,&yhi LDR2 ,&ylo LDR2 ;emit-long JSR2
+    SPACE #3d EMIT SPACE
+    ,&xhi LDR2 ,&xlo LDR2
+    ,&yhi LDR2 ,&ylo LDR2
+    ,&testaddr LDR2 JSR2
+    ,&emitaddr LDR2 JSR2 NEWLINE
+RTN
+&testsym $1
+&testaddr $2
+&emitaddr $2
+&xhi $2 &xlo $2
+&yhi $2 &ylo $2
+
+
+@eq32 ( xhi* xlo* yhi* ylo* -> bool^ )
+    ROT2 EQU2 ,&maybe JCN
+    POP4 #00 RTN
+    &maybe EQU2
+RTN
+
+@ne32 ( xhi* xlo* yhi* ylo* -> bool^ )
+    ROT2 EQU2 ,&maybe JCN
+    POP4 #01 RTN
+    &maybe NEQ2
+RTN
+
+@and32 ( xhi* xlo* yhi* ylo* -> xhi|yhi* xlo|ylo* )
+    ROT2 AND2 TOR2 AND2 SWP2
+RTN
+
+@or32 ( xhi* xlo* yhi* ylo* -> xhi|yhi* xlo|ylo* )
+    ROT2 ORA2 TOR2 ORA2 SWP2
+RTN
+
+@xor32 ( xhi* xlo* yhi* ylo* -> xhi|yhi* xlo|ylo* )
+    ROT2 EOR2 TOR2 EOR2 SWP2
+RTN
+
+@left-by-8 ( x** -> x<<8** )
+    SWP2 ( x2 x3 x0 x1 )
+    SWP POP ( x2 x3 x1 )
+    ROT ROT #00 ( x1 x2 x3 00 )
+RTN
+
+@left-by-16 ( x** -> x<<16** )
+    SWP2 ( x2 x3 x0 x1 )
+    POP2 #0000 ( x2 x3 0000 )
+RTN
+
+@left-by-24 ( x** -> x<<24** )
+    SWP2 POP2 ( x2 x3 )
+    SWP POP #00 #0000 ( x3 00 0000 )
+RTN
+
+@add32 ( xhi* xlo* yhi* ylo* -> zhi* zlo* )
+    ,&y2 STR2 ,&y0 STR2 ( save ylo, yhi )
+    ,&x2 STR2 ,&x0 STR2 ( save xlo, xhi )
+    #0000 #0000 ,&z0 STR2 ,&z2 STR2 ( reset zhi, zlo )
+
+    ( x3 + y3 => z2z3 )
+    #00 ,&x3 LDR #00 ,&y3 LDR ADD2 ,&z2 STR2
+
+    ( x2 + y2 + z2 => z1z2 )
+    #00 ,&x2 LDR ,&z1 LDR2 ADD2 ,&z1 STR2
+    #00 ,&y2 LDR ,&z1 LDR2 ADD2 ,&z1 STR2
+
+    ( x1 + y1 + z1 => z0z1 )
+    #00 ,&x1 LDR ,&z0 LDR2 ADD2 ,&z0 STR2
+    #00 ,&y1 LDR ,&z0 LDR2 ADD2 ,&z0 STR2
+
+    ( x0 + y0 + z0 => z0 )
+    ,&x0 LDR ,&z0 LDR ADD ,&z0 STR
+    ,&y0 LDR ,&z0 LDR ADD ,&z0 STR
+
+    ( load zhi,zlo )
+    ,&z0 LDR2 ,&z2 LDR2
+RTN
+
+( registers for add32 )
+[ &x0 $1 &x1 $1 &x2 $1 &x3 $1 ]
+[ &y0 $1 &y1 $1 &y2 $1 &y3 $1 ]
+[ &z0 $1 &z1 $1 &z2 $2 ]
+
+@mul16 ( x* y* -> z** )
+    ,&y1 STR ,&y0 STR ( save ylo, yhi )
+    ,&x1 STR ,&x0 STR ( save xlo, xhi )
+    #0000 #00 ,&z0 STR2 ,&z2 STR ( reset z0,z1,z2 )
+    #0000 #00 ,&a0 STR2 ,&a2 STR ( reset a0,a1,a2 )
+
+    ( x1 * y1 => z1z2 )
+    #00 ,&x1 LDR #00 ,&y1 LDR MUL2 ,&z1 STR2
+
+    ( x0 * y1 => z0z1 )
+    #00 ,&x0 LDR #00 ,&y1 LDR MUL2 ,&z0 LDR2 ADD2 ,&z0 STR2
+
+    ( x1 * y0 => a1a2 )
+    #00 ,&x1 LDR #00 ,&y0 LDR MUL2 ,&a1 STR2
+
+    ( x0 * y0 => a0a1 )
+    #00 ,&x0 LDR #00 ,&y0 LDR MUL2 ,&a0 LDR2 ADD2 ,&a0 STR2
+
+    ( load z and a )
+    #00 ,&z0 LDR2 ,&z2 LDR
+    ,&a0 LDR2 ,&z2 LDR #00
+    ;add32 JSR2
+RTN
+[ &x0 $1 &x1 $1 ]
+[ &y0 $1 &y1 $1 ]
+[ &z0 $1 &z1 $1 &z2 $2 ]
+[ &a0 $1 &a1 $1 &a2 $2 ]
+
+@mul32 ( x** y** -> z** )
+    ,&y1 STR2 ,&y0 STR2 ( save ylo, yhi )
+    ,&x1 STR2 ,&x0 STR2 ( save xlo, xhi )
+    ,&y1 LDR2 ,&x1 LDR2 ;mul16 JSR2 ( sum = [x1*y1] )
+    ,&y1 LDR2 ,&x0 LDR2 ;mul16 JSR2 ;left-by-16 JSR2 ;add32 JSR2 ( sum += [x0*y1]<<16 )
+    ,&y0 LDR2 ,&x1 LDR2 ;mul16 JSR2 ;left-by-16 JSR2 ;add32 JSR2 ( sum += [x1*y0]<<16 )
+    ( [x0*y0]<<32 will completely overflow )
+RTN
+[ &x0 $2 &x1 $2 ]
+[ &y0 $2 &y1 $2 ]
+
+@emit-long ( hi* lo* -> )
+    SWP2
+    ;emit-short JSR2
+    ;emit-short JSR2
+RTN
+
+@emit-short ( x* -> )
+    SWP ( lo^ hi^ )
+    DUP #04 SFT DIGIT ( emit hi>>4 )
+    #0f AND DIGIT ( emit hi&f )
+    DUP #04 SFT DIGIT ( emit lo>>4 )
+    #0f AND DIGIT ( emit lo&f )
+RTN
+
+@emit-byte ( x^ -> )
+    DUP #04 SFT DIGIT ( emit hi>>4 )
+    #0f AND DIGIT ( emit hi&f )
+RTN
+
+@digits
+    30 31 32 33 34 35 36 37
+    38 39 61 62 63 64 65 66