Added logic operators to ALU

This commit is contained in:
Devine Lu Linvega 2024-04-28 20:13:51 -07:00
parent 0a1b6bfb5c
commit c9e932765a
1 changed files with 6 additions and 2 deletions

View File

@ -47,8 +47,8 @@ device_write(char *s)
char c = *s, *cap = walk(s), **reg = regs + '0'; char c = *s, *cap = walk(s), **reg = regs + '0';
/* phase: ALU */ /* phase: ALU */
if(*reg) { if(*reg) {
switch(c) {
/* clang-format off */ /* clang-format off */
switch(c) {
case '+': for(acc = sint(*reg++); *reg != 0; reg++) acc += sint(*reg); break; case '+': for(acc = sint(*reg++); *reg != 0; reg++) acc += sint(*reg); break;
case '-': for(acc = sint(*reg++); *reg != 0; reg++) acc -= sint(*reg); break; case '-': for(acc = sint(*reg++); *reg != 0; reg++) acc -= sint(*reg); break;
case '*': for(acc = sint(*reg++); *reg != 0; reg++) acc *= sint(*reg); break; case '*': for(acc = sint(*reg++); *reg != 0; reg++) acc *= sint(*reg); break;
@ -57,8 +57,12 @@ device_write(char *s)
case '&': for(acc = sint(*reg++); *reg != 0; reg++) acc &= sint(*reg); break; case '&': for(acc = sint(*reg++); *reg != 0; reg++) acc &= sint(*reg); break;
case '^': for(acc = sint(*reg++); *reg != 0; reg++) acc ^= sint(*reg); break; case '^': for(acc = sint(*reg++); *reg != 0; reg++) acc ^= sint(*reg); break;
case '|': for(acc = sint(*reg++); *reg != 0; reg++) acc |= sint(*reg); break; case '|': for(acc = sint(*reg++); *reg != 0; reg++) acc |= sint(*reg); break;
/* clang-format on */ case '=': for(acc = sint(*reg++); *reg != 0; reg++) acc = acc == sint(*reg); break;
case '!': for(acc = sint(*reg++); *reg != 0; reg++) acc = acc != sint(*reg); break;
case '>': for(acc = sint(*reg++); *reg != 0; reg++) acc = acc > sint(*reg); break;
case '<': for(acc = sint(*reg++); *reg != 0; reg++) acc = acc < sint(*reg); break;
} }
/* clang-format on */
dst_ += snprintf(dst_, 0x10, "%d", acc); dst_ += snprintf(dst_, 0x10, "%d", acc);
return; return;
} }