2021-05-12 21:28:45 -04:00
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#include "uxn.h"
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2021-01-29 14:17:59 -05:00
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2021-01-29 14:35:59 -05:00
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/*
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2023-01-02 09:40:23 -05:00
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Copyright (u) 2022-2023 Devine Lu Linvega, Andrew Alderwick, Andrew Richards
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2021-01-29 14:17:59 -05:00
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Permission to use, copy, modify, and distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE.
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*/
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2023-08-09 16:20:03 -04:00
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/* Registers
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[ . ][ . ][ . ][ L ][ N ][ T ] <
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[ . ][ . ][ . ][ H2 ][ T ] <
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[ L2 ][ N2 ][ T2 ] <
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*/
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2023-08-08 22:53:23 -04:00
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2023-08-09 22:31:33 -04:00
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#define T *ptr
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#define N *(ptr-1)
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#define L *(ptr-2)
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#define T2 PEEK2((ptr-1))
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#define H2 PEEK2((ptr-2))
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#define N2 PEEK2((ptr-3))
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#define L2 PEEK2((ptr-5))
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2023-08-09 22:43:28 -04:00
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#define HALT(c) { return emu_halt(u, ins, c, pc - 1); }
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#define FLIP { s = ins & 0x40 ? &u->wst : &u->rst; }
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#define SET(x, y) { r = s->ptr; if(x > r) HALT(1) r += (x & k) + y; if(r > 254) HALT(2) ptr = s->dat + r - 1; s->ptr = r; }
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#define PUT1(a) { *(ptr) = a; }
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#define PUT1x2(a, b) { *(ptr) = a; *(ptr - 1) = b; }
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#define PUT1x3(a, b, c) { *(ptr) = a; *(ptr - 1) = b; *(ptr - 2) = c; }
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#define PUT2(a) { POKE2(ptr - 1, a) }
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#define PUT2x2(a, b) { POKE2(ptr - 1, a) POKE2(ptr - 3, b) }
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#define PUT2x3(a, b, c) { POKE2(ptr - 1, a) POKE2(ptr - 3, b) POKE2(ptr - 5, c) }
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int
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uxn_eval(Uxn *u, Uint16 pc)
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{
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int t, n, l, r;
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Uint8 *ram = u->ram;
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if(!pc || u->dev[0x0f]) return 0;
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for(;;) {
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int ins = ram[pc++];
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int k = ins & 0x80 ? 0xff : 0;
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Stack *s = ins & 0x40 ? &u->rst : &u->wst;
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Uint8 *ptr = s->dat + s->ptr - 1;
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switch(ins & 0x1f ? ins & 0x3f : ins << 4) {
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/* IMM */
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case 0x000: /* BRK */ return 1;
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case 0x200: /* JCI */ if(!s->dat[--s->ptr]) { pc += 2; break; } /* else fallthrough */
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case 0x400: /* JMI */ pc += PEEK2(ram + pc) + 2; break;
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case 0x600: /* JSI */ SET(0, 2) PUT2(pc + 2) pc += PEEK2(ram + pc) + 2; break;
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case 0x800: /* LIT */ case 0xc00: SET(0, 1) PUT1(ram[pc++]) break;
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case 0xa00: /* LIT2 */ case 0xe00: SET(0, 2) PUT2(PEEK2(ram + pc)) pc += 2; break;
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/* ALU */
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case 0x01: /* INC */ t=T; SET(1, 0) PUT1(t + 1) break;
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case 0x21: /* INC2 */ t=T2; SET(2, 0) PUT2(t + 1) break;
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case 0x02: /* POP */ SET(1,-1) break;
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case 0x22: /* POP2 */ SET(2,-2) break;
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case 0x03: /* NIP */ t=T; SET(2,-1) PUT1(t) break;
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case 0x23: /* NIP2 */ t=T2; SET(4,-2) PUT2(t) break;
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case 0x04: /* SWP */ t=T;n=N; SET(2, 0) PUT1x2(n, t) break;
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case 0x24: /* SWP2 */ t=T2;n=N2; SET(4, 0) PUT2x2(n, t) break;
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case 0x05: /* ROT */ t=T;n=N;l=L; SET(3, 0) PUT1x3(l, t, n) break;
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case 0x25: /* ROT2 */ t=T2;n=N2;l=L2; SET(6, 0) PUT2x3(l, t, n) break;
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case 0x06: /* DUP */ t=T; SET(1, 1) PUT1x2(t, t) break;
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case 0x26: /* DUP2 */ t=T2; SET(2, 2) PUT2x2(t, t) break;
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case 0x07: /* OVR */ t=T;n=N; SET(2, 1) PUT1x3(n, t, n) break;
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case 0x27: /* OVR2 */ t=T2;n=N2; SET(4, 2) PUT2x3(n, t, n) break;
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case 0x08: /* EQU */ t=T;n=N; SET(2,-1) PUT1(n == t) break;
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case 0x28: /* EQU2 */ t=T2;n=N2; SET(4,-3) PUT1(n == t) break;
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case 0x09: /* NEQ */ t=T;n=N; SET(2,-1) PUT1(n != t) break;
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case 0x29: /* NEQ2 */ t=T2;n=N2; SET(4,-3) PUT1(n != t) break;
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case 0x0a: /* GTH */ t=T;n=N; SET(2,-1) PUT1(n > t) break;
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case 0x2a: /* GTH2 */ t=T2;n=N2; SET(4,-3) PUT1(n > t) break;
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case 0x0b: /* LTH */ t=T;n=N; SET(2,-1) PUT1(n < t) break;
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case 0x2b: /* LTH2 */ t=T2;n=N2; SET(4,-3) PUT1(n < t) break;
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case 0x0c: /* JMP */ t=T; SET(1,-1) pc += (Sint8)t; break;
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case 0x2c: /* JMP2 */ t=T2; SET(2,-2) pc = t; break;
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case 0x0d: /* JCN */ t=T;n=N; SET(2,-2) if(n) pc += (Sint8)t; break;
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case 0x2d: /* JCN2 */ t=T2;n=L; SET(3,-3) if(n) pc = t; break;
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case 0x0e: /* JSR */ t=T; SET(1,-1) FLIP SET(0,2) PUT2(pc) pc += (Sint8)t; break;
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case 0x2e: /* JSR2 */ t=T2; SET(2,-2) FLIP SET(0,2) PUT2(pc) pc = t; break;
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case 0x0f: /* STH */ t=T; SET(1,-1) FLIP SET(0,1) PUT1(t) break;
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case 0x2f: /* STH2 */ t=T2; SET(2,-2) FLIP SET(0,2) PUT2(t) break;
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case 0x10: /* LDZ */ t=T; SET(1, 0) PUT1(ram[t]) break;
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case 0x30: /* LDZ2 */ t=T; SET(1, 1) PUT2(PEEK2(ram + t)) break;
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case 0x11: /* STZ */ t=T;n=N; SET(2,-2) ram[t] = n; break;
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case 0x31: /* STZ2 */ t=T;n=H2; SET(3,-3) POKE2(ram + t, n) break;
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case 0x12: /* LDR */ t=T; SET(1, 0) PUT1(ram[pc + (Sint8)t]) break;
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case 0x32: /* LDR2 */ t=T; SET(1, 1) PUT2(PEEK2(ram + pc + (Sint8)t)) break;
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case 0x13: /* STR */ t=T;n=N; SET(2,-2) ram[pc + (Sint8)t] = n; break;
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case 0x33: /* STR2 */ t=T;n=H2; SET(3,-3) POKE2(ram + pc + (Sint8)t, n) break;
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case 0x14: /* LDA */ t=T2; SET(2,-1) PUT1(ram[t]) break;
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case 0x34: /* LDA2 */ t=T2; SET(2, 0) PUT2(PEEK2(ram + t)) break;
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case 0x15: /* STA */ t=T2;n=L; SET(3,-3) ram[t] = n; break;
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case 0x35: /* STA2 */ t=T2;n=N2; SET(4,-4) POKE2(ram + t, n) break;
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case 0x16: /* DEI */ t=T; SET(1, 0) PUT1(DEI(t)) break;
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case 0x36: /* DEI2 */ t=T; SET(1, 1) PUT1x2(DEI(t + 1), DEI(t)) break;
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case 0x17: /* DEO */ t=T;n=N; SET(2,-2) DEO(t, n) break;
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case 0x37: /* DEO2 */ t=T;n=N;l=L; SET(3,-3) DEO(t, l) DEO((t + 1), n) break;
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case 0x18: /* ADD */ t=T;n=N; SET(2,-1) PUT1(n + t) break;
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case 0x38: /* ADD2 */ t=T2;n=N2; SET(4,-2) PUT2(n + t) break;
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case 0x19: /* SUB */ t=T;n=N; SET(2,-1) PUT1(n - t) break;
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case 0x39: /* SUB2 */ t=T2;n=N2; SET(4,-2) PUT2(n - t) break;
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case 0x1a: /* MUL */ t=T;n=N; SET(2,-1) PUT1(n * t) break;
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case 0x3a: /* MUL2 */ t=T2;n=N2; SET(4,-2) PUT2(n * t) break;
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case 0x1b: /* DIV */ t=T;n=N; SET(2,-1) if(!t) HALT(3) PUT1(n / t) break;
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case 0x3b: /* DIV2 */ t=T2;n=N2; SET(4,-2) if(!t) HALT(3) PUT2(n / t) break;
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case 0x1c: /* AND */ t=T;n=N; SET(2,-1) PUT1(n & t) break;
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case 0x3c: /* AND2 */ t=T2;n=N2; SET(4,-2) PUT2(n & t) break;
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case 0x1d: /* ORA */ t=T;n=N; SET(2,-1) PUT1(n | t) break;
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case 0x3d: /* ORA2 */ t=T2;n=N2; SET(4,-2) PUT2(n | t) break;
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case 0x1e: /* EOR */ t=T;n=N; SET(2,-1) PUT1(n ^ t) break;
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case 0x3e: /* EOR2 */ t=T2;n=N2; SET(4,-2) PUT2(n ^ t) break;
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case 0x1f: /* SFT */ t=T;n=N; SET(2,-1) PUT1(n >> (t & 0xf) << (t >> 4)) break;
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case 0x3f: /* SFT2 */ t=T;n=H2; SET(3,-1) PUT2(n >> (t & 0xf) << (t >> 4)) break;
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2021-08-29 17:53:31 -04:00
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}
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2023-06-07 11:03:28 -04:00
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}
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}
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